This invention relates to a MOS (metal oxide film semiconductor) memory circuit, and more particularly to a memory circuit being capable of converting the matrix of a memory array and suitable for the processing of character patterns and graphic patterns.
Although the following description will be made with respect to an N-channel MOS memory circuit, it is self-evident that the description will be likewise applicable to a P-channel MOS memory circuit.
A typical conventional memory circuit is illustrated in FIG. 1. In the memory circuit of FIG. 1, one terminal of each of loads 11 and 12 is connected to a power source 104, the other terminal of the load 11 is connected to the source terminal of a transfer transistor 13, the drain terminal of a driver transistor 15 and the gate terminal of a driver transistor 16, the other terminal of the load 12 is connected to the source terminal of a transfer transistor 14, the gate terminal of the driver transistor 15 and the drain terminal of the driver transistor 16, the source terminals of the driver transistors 15, 16 are connected to a grounding conductor 105, the drain terminals of the transfer transistors 13, 14 are respectively connected to digit lines 102 and 103, and the gate terminals thereof are connected in common to a word line 101.
The operation of this memory circuit will be described with reference to FIG. 2 and FIG. 3. Write operation is effected by applying a high level signal to the word line 101 and applying a low level signal to either the digit line 102 or 103 as illustrated in FIG. 2. Similarly to the write operation, read operation is executed by applying a high level signal to the word line 101 thereby causing one of the digit lines 102 and 103 to sense a signal corresponding to the written signal as illustrated in FIG. 3.
A typical memory array consisting of 4 words.times.4 bits and using the conventional memory circuit is illustrated in FIG. 4. In FIG. 4, CWA1, CWA2, CWA3, and CWA4 denote word lines, CDA1, CDA1 (inversion of CDA1), CDA2, CDA2, CDA3, CDA3, CDA4, and CDA4 denote digit lines, and Cij (i=1 to 4, j32 1 to 4) denotes the memory circuit illustrated in FIG. 1. Writing data in the memory circuit C11, C12, C13, or C14 is executed by applying a high level signal to the word line CWA1 and applying a high level or low level signal to the data line CDAi or CDAi (i=1 to 4). Reading data from the memory circuit is effected by applying a high level to the word line CEA1 and sensing a signal developing on the digit line CDAi or CDAi (i=1 to 4). As is evident from FIG. 4, the data of the memory circuits in row selected by the word line CWAi (i=1 to 4) appear on the digit line CDAi or CDAi (i=1 to 4) but the data of the memory circuits in column Ci1, Ci2, Ci3, or Ci4 (i=1 to 4) cannot be read out all at once. This means that the conventional memory array is incapable of matrix conversion.